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December 28, 2011 Newswires
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U.S. Patents Awarded to Inventors in New York (Dec. 28)

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ALEXANDRIA, Va., Dec. 28 -- The following federal patents were awarded to inventors in New York.

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International Business Machines Assigned Patent for Fuzzy Multi-level Security

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,087,090) developed by nine co-inventors for a fuzzy multi-level security. The co-inventors are Pau-Chen Cheng, Yorktown Heights, N.Y., Shai Halevi, Elmsford, N.Y., Trent Ray Jaeger, Croton-on-Hudson, N.Y., Paul Ashley Karger, Chappaqua, N.Y., Ronald Perez, Mount Kisco, N.Y., Pankaj Rohatgi, New Rochelle, N.Y., Angela Marie Schuett, Columbia, Md., Michael Steiner, New York, and Grant M. Wagner, Columbia, Md.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An access control system and method includes a risk index module which computes a risk index for a dimension contributing to risk. A boundary range defined for a parameter representing each risk index such that the parameter above the range is unacceptable, below the range is acceptable and in the range is acceptable with mitigation measures. A mitigation module determines the mitigation measures which reduce the parameter within the range by mapping the effectiveness of performing the mitigation measures to determine a residual risk after a mitigation measure has been implemented."

The patent application was filed on June 2, 2008 (12/131,206). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,090&OS=8,087,090&RS=8,087,090

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

Eastman Kodak Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- Eastman Kodak, Rochester, N.Y., has been assigned a patent (8,087,054) developed by five co-inventors for an "automated event content processing method and system." The co-inventors are Carolyn A. Zacks, Rochester, N.Y., Michael J. Telek, Pittsford, N.Y., Frank Marino, Rochester, N.Y., Dan Harel, Rochester, N.Y., and Douglas B. Beaudet, Geneseo, N.Y.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for organizing event content in the form of electronic signals is provided. In accordance with this method an event profile is determined. The event content is obtained and the event content is organized based upon the event profile."

The patent application was filed on Sept. 30, 2002 (10/260,975). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,054&OS=8,087,054&RS=8,087,054

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

Uniloc USA Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- Uniloc USA, Irvine, Calif., has been assigned a patent (8,087,092) developed by five co-inventors for a "method and apparatus for detection of tampering attacks." The co-inventors are Ric B. Richardson, Irvine, Calif., Casey S. Potenzone, Los Angeles, Benjamin T. Abraham, New York, Farza Angha, San Francisco, and Hamid R. Younessi, New York.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for detecting an attempted attack on a security system. In one preferred embodiment of the present invention, the method includes the step of retrieving a parameter from a hardware system, wherein the parameter changes during an operation of the hardware system. Then, comparing the retrieved parameter with a previously stored parameter; and, detecting a lack of change between the retrieved parameter and the previously stored parameter. An apparatus and an article of manufacture for detecting an attempted attack on a security system is also disclosed."

The patent application was filed on Sept. 5, 2006 (11/470,235). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,092&OS=8,087,092&RS=8,087,092

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

International Business Machines Assigned Patent for Authentication Method and System

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,087,071) developed by Wayne Michael Delia, Poughkeepsie, N.Y., Edward Emile Kelley, Wappingers Falls, N.Y., and Franco Motika, Hopewell Junction, N.Y., for an "authentication method and system."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An authentication method and system. A computing system generates an authentication table associated with a user. The computing system receives first authentication data and second authentication data differing from the first authentication data. The first authentication data and the second authentication data are placed in the authentication table. The authentication table comprising the first authentication data and the second authentication data is stored in the computing system. The computing system generates an action table. The computing system receives first action data and second action data and places the first action data and the second action data in the action table. The action table comprising the first action data and the second action data is stored in the computing system."

The patent application was filed on Dec. 5, 2008 (12/329,229). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,071&OS=8,087,071&RS=8,087,071

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

Medco Health Solutions Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- Medco Health Solutions, Franklin Lakes, N.J., has been assigned a patent (8,086,472) developed by seven co-inventors for an "apparatus and method for managing prescription benefits." The co-inventors are Jeffrey H. Alexander, Flemington, N.J., William J. Jackson, West Orange, N.J., Glen D. Stettin, Upper Saddle River, N.J., Mark A. Carlson, Westerville, Ohio, Nicholas C. Taylor, Upper Arlington, Ohio, Zev Juravel, New Hempstead, N.Y., and Richard P. Healy, Bronxville, N.Y.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method are disclosed for managing prescription benefits. Case records containing information regarding patients and prescription coverage activities for the patients are stored in the system. Users are allowed access to the system via an appropriate electronic communication network. The user can subsequently perform various tasks in order to maintain and review coverage activities. The user can also enter additional prescription coverage activities into the case records, as well as verify that information entered into the case records has been updated."

The patent application was filed on Aug. 10, 2010 (12/853,596). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,472&OS=8,086,472&RS=8,086,472

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

moka5 Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- moka5, Redwood City, Calif., has been assigned a patent (8,087,017) developed by four co-inventors for a "trace-assisted prefetching of virtual machines in a distributed system." The co-inventors are John C. Whaley, San Mateo, Calif., Won-Suk Chun, Manhasset, N.Y., Monica Sin-Ling Lam, Menlo Park, Calif., and Constantine P. Sapuntzakis, Mountain View, Calif.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The disclosed implementations related to prefetching of virtual machines. Some embodiments can receive a virtual disk including a first page table block corresponding to one or more other page table blocks or one or more data blocks. Next, the embodiments can generate a representation of the first page table block, the representation of the first page table block including presence information with respect to the one or more other page table blocks or the one or more data blocks in the virtual disk that are pointed to by the first page table block. The embodiments can then sign the representation of the first page table block. Next, the embodiments can use the signature and the generated position independent representation to verify the integrity of the first page table block, and/or change the offset of the one or more other page table blocks or the one or more data blocks."

The patent application was filed on April 9, 2008 (12/100,238). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,017&OS=8,087,017&RS=8,087,017

Hemanta Panigrahi.

***

International Business Machines Assigned Patent for Domain Stretching for an Advanced Dual-representation Polyhedral Loop Transformation Framework

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,087,011) developed by four co-inventors for a "domain stretching for an advanced dual-representation polyhedral loop transformation framework." The co-inventors are Alexandre E. Eichenberger, Chappaqua, N.Y., John K.P. O'Brien, South Salem, N.Y., Kathryn M. O'Brien, South Salem, N.Y., and Nicolas T. Vasilache, Ridgewood, N.J.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Mechanisms for domain stretching for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for stretching the domains of statements in a program loop view of the source code to thereby normalize the domains."

The patent application was filed on Sept. 26, 2007 (11/861,503). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,011&OS=8,087,011&RS=8,087,011

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

International Business Machines Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,988) developed by nine co-inventors for a "chip design and fabrication method optimized for profit." The co-inventors are Nathan Buck, Underhill, Vt., Howard H. Chen, Yorktown Heights, N.Y., James P. Eckhardt, Pleasant Valley, N.Y., Eric A. Foreman, Fairfax, Vt., James C. Gregerson, Hyde Park, N.Y., Peter A. Habitz, Hinesburg, Vt., Susan K. Lichtensteiger, Essex Junction, Vt., Chandramouli Visweswariah, Croton-On-Hudson, N.Y., and Tad J. Wilder, South Hero, Vt.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips."

The patent application was filed on May 18, 2009 (12/467,326). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,988&OS=8,086,988&RS=8,086,988

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

AT&T Intellectual Property II Assigned Patent for Network-based Service to Provide On-demand Video Summaries of Television Programs

ALEXANDRIA, Va., Dec. 28 -- AT&T Intellectual Property II, Atlanta, has been assigned a patent (8,087,049) developed by Vijay K. Bhagavath, Lincroft, N.J., Robert Edward Markowitz, Glen Rock, N.J., and Joseph Thomas O'Neil, Staten Island, N.Y., for a "network-based service to provide on-demand video summaries of television programs."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A network-based device allows customers to receive television programming and to view summaries of the programming. A method of providing the summaries comprises: dividing a received program into program segments each identified by index marks, summarizing each program segment into summary segments identified by similar index marks, generating metadata files for delimiting a beginning and an end of summary segments and program segments, storing the summary segments and accessing the summary segments to supply the summary segments in lieu of program segments upon demand."

The patent application was filed on June 4, 2010 (12/793,994). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,049&OS=8,087,049&RS=8,087,049

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

International Business Machines Assigned Patent for Selective Code Generation Optimization for an Advanced Dual-representation Polyhedral Loop Transformation Framework

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,087,010) developed by four co-inventors for a "selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework." The co-inventors are Alexandre E. Eichenberger, Chappaqua, N.Y., John K.P. O'Brien, South Salem, N.Y., Kathryn M. O'Brien, South Salem, N.Y., and Nicolas T. Vasilache, Ridgewood, N.J.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Mechanisms for selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization."

The patent application was filed on Sept. 26, 2007 (11/861,493). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,010&OS=8,087,010&RS=8,087,010

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

International Business Machines Assigned Patent for Fair Share Scheduling Based on an Individual User's Resource Usage and the Tracking of that Usage

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,087,026) developed by Enci Zhong, Poughkeepsie, N.Y., for a "fair share scheduling based on an individual user's resource usage and the tracking of that usage."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Fair share scheduling to divide the total amount of available resource into a finite number of shares and allocate a portion of the shares to an individual user or group of users as a way to specify the resource proportion entitled by the user or group of users. The scheduling priority of jobs for a user or group of users depends on a customizable expression of allocated and used shares by that individual user or group of users. The usage by the user or group of users is accumulated and an exponential decay function is applied thereto in order to keep track of historic resource usage for a user or group of users by one piece of data and an update timestamp."

The patent application was filed on April 27, 2006 (11/412,758). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,026&OS=8,087,026&RS=8,087,026

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

AT&T Intellectual Property II Assigned Patent for Methods and Apparatus for Rapid Acoustic Unit Selection from a Large Speech Corpus

ALEXANDRIA, Va., Dec. 28 -- AT&T Intellectual Property II, Atlanta, has been assigned a patent (8,086,456) developed by Mark Charles Beutnagel, Mendham, N.J., Mehryar Mohri, New York, and Michael Dennis Riley, New York, for "methods and apparatus for rapid acoustic unit selection from a large speech corpus."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A speech synthesis system can select recorded speech fragments, or acoustic units, from a very large database of acoustic units to produce artificial speech. The selected acoustic units are chosen to minimize a combination of target and concatenation costs for a given sentence. However, as concatenation costs, which are measures of the mismatch between sequential pairs of acoustic units, are expensive to compute, processing can be greatly reduced by pre-computing and caching the concatenation costs. Unfortunately, the number of possible sequential pairs of acoustic units makes such caching prohibitive. A method for constructing an efficient concatenation cost database is provided by synthesizing a large body of speech, identifying the acoustic unit sequential pairs generated and their respective concatenation costs. By constructing a concatenation cost database in this fashion, the processing power required at run-time is greatly reduced with negligible effect on speech quality."

The patent application was filed on July 20, 2010 (12/839,937). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,456&OS=8,086,456&RS=8,086,456

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

Intuit, Ingenix Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- Intuit, Mountain View, Calif., and Ingenix, Eden Prairie, Minn., have been assigned a patent (8,086,474) developed by seven co-inventors for a "managing insurance claim data." The co-inventors are Craig M. Lasalle, Los Altos, Calif., Lisa H. Rogers, Palo Alto, Calif., Ellen Linardi, Santa Clara, Calif., Beth Goldman, San Francisco, Lavanya Elangovan, San Jose, Calif., Maureen Costello, Clarence, N.Y., and Matthew J. Homier, San Francisco.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for managing insurance claim data involves identifying a first insurance claim data and a second insurance claim data using pattern recognition on multiple insurance claim data associated with an insured party, where the first insurance claim data and the second insurance claim data are associated with a single insurance claim associated with the insured party, where the second insurance claim data is later in time than the first insurance claim data, and where the second insurance claim data includes a modification of the single insurance claim relative to the first insurance claim data. The method further involves determining a financial responsibility of the insured party for the single insurance claim based on the second insurance claim data, and presenting the first insurance claim data, the second insurance claim data, and the financial responsibility in a graphical user interface (GUI)."

The patent application was filed on July 30, 2007 (11/830,813). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,474&OS=8,086,474&RS=8,086,474

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

International Business Machines Assigned Patent for Topology Aware Grid Services Scheduler Architecture

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,087,023) developed by James Robert Harold Challenger, Carrison, N.Y., and Marcos Novaes, Hopewell Junction, N.Y., for "topology aware grid services scheduler architecture."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The invention provides a system/method of processing client requests over a computer network of hosts, that includes creating persistent containers in the hosts, creating objects in the containers, grouping the containers into grid container arrays, grouping objects within containers that are within a single grid container array into grid object arrays, creating one micro scheduler for each grid container array, dividing each of the client requests into a plurality of tasks, and assigning groups of the tasks to the microschedulers, wherein the microschedulers assign individual tasks to the objects. The invention assigns the microschedulers additional groups of tasks as the microschedulers return groups of completed tasks. The method can also include passing the client requests through gateways to multiple grid services schedulers."

The patent application was filed on March 19, 2008 (12/051,050). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,087,023&OS=8,087,023&RS=8,087,023

Written by Satyaban Rath; edited by Hemanta Panigrahi.

***

International Business Machines Assigned Patent for Healthcheck of Information Technology Infrastructure Based on Log Data

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,596) developed by seven co-inventors for a "healthcheck of information technology infrastructure based on log data." The co-inventors are Fausto Bernardini, New York, Rong N. Chang, Pleasantville, N.Y., Chang-Shing Perng, Goldens Bridge, N.Y., Edward C. So, Flushing, N.Y., Chunqiang Tang, Ossining, N.Y., Tao Tao, Briarcliff Manor, N.Y., and Chun Zhang, Ossining, N.Y.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Checking health of information technology infrastructure based on log data, in one aspect, may collect log data non-intrusively from a production system, said log data at least associated with transactions occurring in the production system and resource utilization of the production system, may normalize said log data into a plurality of log data types, may perform data regression analysis using said plurality of log data types to estimate resources consumed by each of said transactions and throughput of each of said transactions, and may use a queuing model to predict performance of the information technology infrastructure under various workloads."

The patent application was filed on May 15, 2008 (12/121,301). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,86,596.PN.&OS=PN/80,86,596&RS=PN/80,86,596

Written by Ruby Maibam; edited by Jaya Anand.

***

International Business Machines ssigned Patent for Unified Collection of Content Analytic Data

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,577) developed by eight co-inventors for a "unified collection of content analytic data." The co-inventors are John Hans Handy-Bosma, Cedar Park, Texas, Kevin Holubar, Austin, Texas, Shannon James Kerlick, Cedar Park, Texas, Dan Jeffrey Mandelstein, Austin, Texas, Arvind Raveendranathan Nair, Bangalore, India, Mei Yang Selvage, Austin, Texas, Thomas Christopher Storey, Wappingers Falls, N.Y., and Sudhandhira Selvan Viswanathan, Bangalore, India.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A user evaluation of distributed content comprising an Evaluation Program (EP) that creates a user session when a user accesses distributed content is stored. The user evaluation is saved with other information such as the time and date of the evaluation, the user's personal information, and the navigation path the user used to access the distributed content page. The EP records the user's navigation of the distributed content in the user session. The EP gives the user the opportunity to rate distributed content. The EP saves the user's evaluation with the user session data and external stimuli data. The EP closes the user session when the user leaves the distributed content. The EP reopens the user session when the user returns to the distributed content."

The patent application was filed on Dec. 18, 2007 (11/959,265). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,86,577.PN.&OS=PN/80,86,577&RS=PN/80,86,577

Written by Ruby Maibam; edited by Jaya Anand.

***

Goldman Sachs Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- Goldman Sachs, New York, has been assigned a patent (8,086,617) developed by J. Gilmore Childers, Summit, N.J., and David Lawrence, New York, for a "link analysis mapping program risk management."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system for managing risk by indicating links between one or more persons or entities which can include a process that gathers information about individuals and organizations into a computerized system where it can be analyzed to associate one or more individuals or organizations with links to other individuals or organizations. A user can designate a person or entity and the system will provide an indication of linkages associated with the designated person. Some embodiments can include a user specifying a particular type of link or limit links to a specified degree of separation between the designated person and any other person or entity."

The patent application was filed on May 21, 2010 (12/785,387). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,86,617.PN.&OS=PN/80,86,617&RS=PN/80,86,617

Written by Ruby Maibam; edited by Jaya Anand.

***

International Business Machines Assigned Patent for Optimizations of a Perform Frame Management Function Issued by Pageable Guests

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,811) developed by five co-inventors for "optimizations of a perform frame management function issued by pageable guests." The co-inventors are Charles W. Gainey Jr., Poughkeepsie, N.Y., Dan F. Greiner, San Jose, Calif., Lisa Cranton Heller, Rhinebeck, N.Y., Damian L. Osisek, Vestal, N.Y., and Gustav E. Sittmann III, Webster Groves, Mo.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests."

The patent application was filed on Feb. 25, 2008 (12/036,725). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,811.PN.&OS=PN/8,086,811&RS=PN/8,086,811

Written by Arpi Sharma; edited by Anand Kumar.

***

CommVault Systems Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- CommVault Systems, Oceanport, N.J., has been assigned a patent (8,086,809) developed by four co-inventors for an "interface systems and methods for accessing stored data." The co-inventors are Anand Prahlad, East Brunswick, N.J., Randy De Meno, Staten Island, N.Y., Jeremy A. Schwartz, Red Bank, N.J., and James J. McGuigan, Avon, N.J.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A modular data and storage management system. The system includes a time variance interface that provides for storage into a storage media of data that is received over time. The time variance interface of the modular data and storage management system provides for retrieval, from the storage media, of an indication of the data corresponding to a user specified date. The retrieved indication of the data provides a user with an option to access specific information relative to the data, such as content of files that are included in the data."

The patent application was filed on Sept. 20, 2010 (12/886,496). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,809.PN.&OS=PN/8,086,809&RS=PN/8,086,809

Written by Arpi Sharma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Methods and Apparatus for Perturbing an Evolving Data Stream for Time Series Compressibility and Privacy

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,655) developed by Philip Shi-Lung Yu, Chappaqua, N.Y., and Spyridon Papadimitriou, White Plains, N.Y., for "methods and apparatus for perturbing an evolving data stream for time series compressibility and privacy."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques for perturbing an evolving data stream are provided. The evolving data stream is received. An online linear transformation is applied to received values of the evolving data stream generating a plurality of transform coefficients. A plurality of significant transform coefficients are selected from the plurality of transform coefficients. Noise is embedded into each of the plurality of significant transform coefficients, thereby perturbing the evolving data stream. A total noise variance does not exceed a defined noise variance threshold." The patent application was filed on Sept. 14, 2007 (11/855,378). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,655&OS=8,086,655&RS=8,086,655

Written by Arpi Sharma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for High Availability Memory System

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,783) developed by four co-inventors for a "high availability memory system." The co-inventors are James A. O'Connor, Ulster Park, N.Y., Kevin C. Gower, LaGrangeville, N.Y., Luis A. Lastras-Montano, Cortlandt Manor, N.Y., and Warren E. Maule, Cedar Park, Texas.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A memory system with high availability is provided. The memory system includes multiple memory channels. Each memory channel includes at least one memory module with memory devices organized as partial ranks coupled to memory device bus segments. Each partial rank includes a subset of the memory devices accessible as a subchannel on a subset of the memory device bus segments. The memory system also includes a memory controller in communication with the multiple memory channels. The memory controller distributes an access request across the memory channels to access a full rank. The full rank includes at least two of the partial ranks on separate memory channels. Partial ranks on a common memory module can be concurrently accessed. The memory modules can use at least one checksum memory device as a dedicated checksum memory device or a shared checksum memory device between at least two of the concurrently accessible partial ranks."

The patent application was filed on Feb. 23, 2009 (12/390,731). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,783.PN.&OS=PN/8,086,783&RS=PN/8,086,783

Written by Arpi Sharma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Community-defined and Managed Communication Network

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,680) developed by Irwin Boutboul, Jersey City, N.J., Albert Delucca, Wantagh, N.Y., and Jean-David C. Gibrat, New York, for a "community-defined and managed communication network."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A community-defined and managed communication network is provided. The community-defined and managed network includes creating a profile for a user of the network that includes a user-selected attribute and identifying a relationship between the attribute in the profile and data external to the profile. The identification includes analyzing user community-generated descriptors of the attribute and searching the external data for common descriptors. The community-defined and managed network further includes initiating an activity responsive to the analysis, which includes one or more of: prompting the user to invite a second user who is not a registered member of the communication network to join the communication network; prompting a third user to evaluate the user with respect to the attribute; and prompting the user to initiate a communication with a fourth user who is a registered member of the communication network."

The patent application was filed on Nov. 14, 2008 (12/271,001). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,680.PN.&OS=PN/8,086,680&RS=PN/8,086,680

Written by Arpi Sharma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Support for Non-locking Parallel Reception of Packets Belonging to a Single Memory Reception FIFO

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,766) developed by six co-inventors for a "support for non-locking parallel reception of packets belonging to a single memory reception FIFO." The co-inventors are Dong Chen, Yorktown Heights, N.Y., Philip Heidelberger, Yorktown Heights, N.Y., Valentina Salapura, Yorktown Heights, N.Y., Robert M. Senger, Yorktown Heights, N.Y., Burkhard Steinmacher-Burow, Boeblingen, Germany, and Yutaka Sugawara, Yorktown Heights, N.Y.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-locking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory."

The patent application was filed on Jan. 15, 2010 (12/688,747). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,766.PN.&OS=PN/8,086,766&RS=PN/8,086,766

Written by Arpi Sharma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Structure for Fractional-N Phased-lock-loop (PLL) System

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,974) developed by Kai Di Feng, Hopewell Junction, N.Y., for a "structure for fractional-N phased-lock-loop (PLL) system."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. A method in a computer-aided design system for generating a functional design model of a fractional-N phased-lock-loop (PLL) structure is provided in one embodiment. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit is presented in another embodiment."

The patent application was filed on July 21, 2008 (12/176,536). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,974&OS=8,086,974&RS=8,086,974

Written by Kusum Sangma; edited by Anand Kumar.

***

International Business Machines Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,980) developed by Dieu Q. Phan Vogel, Fishkill, N.Y., for an "efficient power region checking of multi-supply voltage microprocessors."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A improved method for very-early validation of voltage region physical power distribution networks uses initial floor plan and early power grid data to identify physical power connection problems associated with voltage regions defined in multi-supply voltage microprocessor chip designs. Since all checking algorithms are floor plan-based and do not require complete circuit data, they are executable very early in the design phase. As a result, power region-related problems can be resolved much sooner than by using conventional full-chip physical design checking and power grid analysis methods."

The patent application was filed on Feb. 15, 2008 (12/032,276). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,980&OS=8,086,980&RS=8,086,980

Written by Kusum Sangma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Method, Apparatus, and Computer Program Product for Coordinating Error Reporting and Reset Utilizing an I/O Adapter That Supports Virtualization

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,903) developed by five co-inventors for a "method, apparatus, and computer program product for coordinating error reporting and reset utilizing an I/O adapter that supports virtualization." The co-inventors are Richard Louis Arndt, Austin, Texas, Patrick Allen Buckland, Austin, Texas, Harvey Gene Kiel, Rochester, Minn., Renato John Recio, Austin, Texas, and Jaya Srikrishnan, Wappingers Falls, N.Y. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method, apparatus, and computer program product are disclosed in a shared processor data processing system for coordinating error reporting for and resetting of a physical I/O adapter that supports virtualization. The physical I/O adapter is virtualized by generating virtual I/O adapters that each represent a portion of the physical I/O adapter. Each one of the virtual I/O adapters is assigned to a different one of client logical partitions. A determination is made regarding whether the physical I/O adapter may have experienced an error. If the physical I/O adapter has experienced an error, all of the client logical partitions are notified about the error and a recovery of the physical I/O adapter is coordinated among all of the client logical partitions by waiting for each client logical partition to acknowledge the error notification before the physical I/O adapter is reset."

The patent application was filed on March 31, 2008 (12/059,870). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,903&OS=8,086,903&RS=8,086,903

Written by Kusum Sangma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Methods for Statistical Slew Propagation During Block-based Statistical Static Timing Analysis

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,976) developed by Jeffrey G. Hemmett, St. George, Vt., Chandramouli Visweswariah, Croton-on-Hudson, N.Y., and Vladimir Zolotov, Putnam Valley, N.Y., for "methods for statistical slew propagation during block-based statistical static timing analysis."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew at the first corner. The method further includes perturbing the canonical approximation of the input slew to a different corner, calculating a delay and an output slew at the different corner using the perturbed input slew canonical, and determining a sensitivity of the delay and the output slew to a plurality of parameters, simultaneous with implicit sensitivity calculations to the input slew, with finite difference calculations between the first corner and perturbed data."

The patent application was filed on May 15, 2008 (12/121,023). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,976&OS=8,086,976&RS=8,086,976

Written by Kusum Sangma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Performing Cryptographic Provider Failover

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,843) developed by Sarah Blodgett Hughes, Wappingers Falls, N.Y., and Jason Greg Katonica, Poughkeepsie, N.Y., for a "performing cryptographic provider failover."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Cryptographic provider failover is performed. Upon receipt of a first security request, an integrated cryptographic provider constructs a table including a list of underlying cryptographic providers for service type algorithm pairs. The integrated cryptographic provider is one of the underlying cryptographic providers in the list. The underlying cryptographic providers are registered as hardware and software cryptographic providers in the list. The integrated cryptographic provider is registered as a routing cryptographic provider in the list. The list is arranged so that the integrated cryptographic provider has the highest priority. The integrated cryptographic provider specifies fai lover support for all registered service type algorithm pairs using one or more of the underlying cryptogaphic providers. In response to a subsequent security request, the integrated cryptographic utilizes the list of the underlying cryptographic providers to identify a second cryptographic provider to which the request will be routed if a first cryptographic provider fails."

The patent application was filed on Sept. 24, 2007 (11/860,130). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8086843.PN.&OS=PN/8086843&RS=PN/8086843

Written by Kusum Sangma; edited by Anand Kumar.

***

Google Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- Google, Mountain View, Calif., has been assigned a patent (8,086,953) developed by four co-inventors for an "identifying transient portions of web pages." The co-inventors are Eran Gabber, Summit, N.J., Michael Flaster, Tenafly, N.Y., Ruoming Pang, Jersey City, N.J., and Shanmugavelayutham Muthukrishnan, New York. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems, methods and computer readable media for identifying transient content in web pages. Transient content can be identified, for example, by parsing different versions of the same web page into tokens, and inserting fingerprints associated with the tokens into data structures. The data structures can be compared to each other to identify differences between the web pages, thereby identifying transient content associated with the web pages."

The patent application was filed on Dec. 19, 2008 (12/340,343). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,953&OS=8,086,953&RS=8,086,953

Written by Kusum Sangma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Methods for Characterizing Device Variation in Electronic Memory Circuits

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,917) developed by Ching-Te K. Chuang, South Salem, N.Y., Jae-Joon Kim, Austin, Texas, and Saibal Mukhopadhyay, Atlanta, for "methods for characterizing device variation in electronic memory circuits."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, .DELTA., between their gate-to-source voltages, and (ii) vary the .DELTA. until the comparator circuit output toggles from the first digital logical level to the second digital logical level."

The patent application was filed on Aug. 17, 2009 (12/542,187). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,917&OS=8,086,917&RS=8,086,917

Written by Kusum Sangma; edited by Anand Kumar.

***

VMware Assigned Patent

ALEXANDRIA, Va., Dec. 28 -- VMware, Palo Alto, Calif., has been assigned a patent (8,086,822) developed by four co-inventors for an "in-place shadow tables for virtualization." The co-inventors are Scott W. Devine, Katanah, N.Y., Lawrence S. Rogel, Brookline, Mass., Prashanth P. Bungale, Cambridge, Mass., and Gerald A. Fry, Brighton, Mass. The abstract of the patent published by the U.S. Patent and Trademark Office states: "In a computing system having virtualization software including a guest operating system (OS), a method for providing page tables that includes: providing a guest page table used by the guest OS and a shadow page table used by the virtualization software wherein at least a portion of the guest page table and the shadow page table share computer memory."

The patent application was filed on May 14, 2009 (12/466,159). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8086822.PN.&OS=PN/8086822&RS=PN/8086822

Written by Kusum Sangma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Implementing Diagnosis of Transitional Scan Chain Defects Using Logic Built in Self Test LBIST Test Patterns

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,924) developed by Donato Orazio Forlenza, Hopewell Junction, N.Y., Orazio Pasquale Forlenza, Hopewell Junction, N.Y., and Phong T. Tran, Highland, N.Y., for an "implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patterns."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system."

The patent application was filed on Oct. 13, 2008 (12/250,085). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,924&OS=8,086,924&RS=8,086,924

Written by Kusum Sangma; edited by Anand Kumar.

***

International Business Machines Assigned Patent for Performing Error Correction at a Memory Device Level that is Transparent to a Memory Channel

ALEXANDRIA, Va., Dec. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,086,936) developed by Kevin C. Gower, LaGrangeville, N.Y., and Warren E. Maule, Cedar Park, Texas, for a "performing error correction at a memory device level that is transparent to a memory channel."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code."

The patent application was filed on Aug. 31, 2007 (11/848,354). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,086,936&OS=8,086,936&RS=8,086,936

Written by Kusum Sangma; edited by Anand Kumar.

For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com.

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  • Two industry finance experts join National Life Group amid accelerated growth
  • National Life Group Announces Leadership Transition at Equity Services, Inc.
  • SandStone Insurance Partners Welcomes Industry Veteran, Rhonda Waskie, as Senior Account Executive
  • Springline Advisory Announces Partnership With Software And Consulting Firm Actuarial Resources Corporation
  • Insuraviews Closes New Funding Round Led by Idea Fund to Scale Market Intelligence Platform
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